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NLSF3T125 Quad Bus Buffer
with 3-State Control Inputs
The NLSF3T125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The NLSF3T125 requires the 3-state control input (OE) to be set High to place the output into the high impedance state. The T125 inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The NLSF3T125 input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
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QFN-16 CASE 485G
MARKING DIAGRAM
16 1
XXX ALYW
* * * * * * * * * * *
High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model; > 2000 V, Machine Model; > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates
Active-Low Output Enables
A1 OE1 A2 OE2 A3 OE3 A4 OE4 16 15 4 3 8 9 12 13 10 Y4 7 Y3 5 Y2 1 Y1
(Top View) A WL Y WW = Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device NLSF3T125MNR2 Package QFN-16 Shipping 3000 Units/ Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
FUNCTION TABLE
NLSF3T125 Inputs A H L X OE L L H Output Y H L Z .
Figure 1. Logic Diagram
(c) Semiconductor Components Industries, LLC, 2004
1
March, 2004 - Rev. 2
Publication Order Number: NLSF3T125/D
NLSF3T125
A1 16 Y1 NC OE2 A2 OE1 VCC 15 14 OE4 13 A4 NC Y4 OE3 Exposed Pad (EP)
1 2 3 4 5 Y2 6 7 8 A3
12 11 10 9
GND Y3
Figure 2. QFN - 16 Pinout (Top View)
II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII II III II I IIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol VCC Vin Parameter Value Unit DC Supply Voltage DC Input Voltage - 0.5 to + 7.0III V - 0.5 to + 7.0III V V Vout IIK DC Output Voltage Output in 3-State High or Low State - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 20 20 25 75 500 Input Diode Current mA mA mA mA IOK Iout Output Diode Current (VOUT < GND; VOUT > VCC) DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature QFN Packages mW C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Tstg - 65 to + 150 Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin
Parameter
Min 2.0 0 0 0
Max 5.5 5.5
Unit V V V
DC Supply Voltage DC Input Voltage
Vout TA
DC Output Voltage
Output in 3-State High or Low State
5.5 VCC
Operating Temperature
- 40 0
+ 85 20
C
tr, tf
Input Rise and Fall Time
VCC = 5.0 V 0.5 V
ns/V
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II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II I IIIII II II II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II I IIIII II II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II I IIIII II II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II I II II II II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I II I II I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII I II I IIIII I II I II I IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II II II I I I I I I I I I II I IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II I IIIII II II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIII II I IIIII I II II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I I I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I IIIIIIIIIIIIIIIII I I I III II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
DC ELECTRICAL CHARACTERISTICS
Symbol IOPD ICCT VOH VOL VIH ICC IOZ VIL IIN Output Leakage Current Maximum 3-State Leakage Current Quiescent Supply Current Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage g VIN = VIH or VIL Minimum High-Level Output Voltage g VIN = VIH or VIL Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter VOUT = 5.5 V VIN = VIH or VIL VOUT = VCC or GND Input: VIN = 3.4 V VIN = VCC or GND VIN = 5.5 V or GND VIN = VIH or VIL IOL = 2.0 mA IOL = 4.0 mA IOL = 8.0 mA VOL @ IOL, 50 mA VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = - 2.0 mA IOH = - 4.0 mA IOH = - 8.0 mA VOL @ IOL, 50 mA VIN = VIH or VIL IOH = - 50 mA 2.3 V 0.3 V 3.3 V 0.3 V 5.0 V 0.5 V 2.3 V 0.3 V 3.3 V 0.3 V 5.0 V 0.5 V Test Conditions VCC (V) 0.0 5.5 5.5 5.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 0 to 5.5 0.5 VCC 0.4 VCC 0.44 VCC
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NLSF3T125
1.82 2.58 3.94
MinIII Max TypIII
1.9 2.9 4.4
TA = 25C
3 0.0 0.0 0.0 2.0 3.0 4.5 0.3 VCC 0.18 VCC 0.18 VCC 0.25 0.1 1.35 0.36 0.36 0.36 0.5 2.0 0.1 0.1 0.1 0.5 VCC 0.4 VCC 0.44 VCC 1.72 2.48 3.80 Min 1.9 2.9 4.4 TA 85C 0.3 VCC 0.18 VCC 0.18 VCC 1.0 1.50 0.44 0.44 0.44 Max 2.5 5.0 0.1 0.1 0.1 20 0.5 VCC 0.4 VCC 0.44 VCC 1.60 2.34 3.66 Min 1.9 2.9 4.4 TA 125C 0.3 VCC 0.18 VCC 0.18 VCC 1.0 1.65 0.52 0.52 0.52 Max 2.5 0.1 0.1 0.1 10 40 Unit mA mA mA mA mA V V V V
II I I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I II I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I III I I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I I IIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I II I I I II III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIII IIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol tOSLH, tOSHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Cout Cin Power Dissipation Capacitance (Note 2) Maximum Three-State Output Capacitance (Output in High Impedance State) Maximum Input Capacitance Output-to-Output Skew Maximum Output Disable Time OE to Y Time,OE Maximum Output Enable TIme OE to Y TIme,OE Maximum Propagation Delay, A to Y Parameter VCC = 5.0 0.5 V CL = 50 pF (Note 1) VCC = 3.3 0.3 V CL = 50 pF (Note 1) VCC = 5.0 0.5 V CL = 50 pF RL = 1.0 kW VCC = 3.3 0.3 V CL = 50 pF RL = 1.0 kW VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF RL = 1.0 kW VCC = 3.3 0.3 V CL = 15 pF RL = 1.0 kW CL = 50 pF VCC = 2.3 0.3 V CL = 15 pF VCC = 2.3 0.3 V CL = 15 pF VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF VCC = 3.3 0.3 V CL = 15 pF CL = 50 pF VCC = 2.3 0.3 V CL = 15 pF Test Conditions
1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
CPD
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NLSF3T125
4 MinIII Typ Max 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0III 14.5 16.9 TA = 25C 15.4 14.8 6.1 9.5 3.6 5.1 5.4 7.9 3.8 5.3 5.6 8.1 6 4 13.2 18.0 16.2 8.0 11.5 8.0 11.5 1.0 1.5 8.8 5.1 7.1 5.5 7.5 10 Typical @ 25C, VCC = 5.0V TA = 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 9.5 13.0 9.5 13.0 10.0 15.0 19.8 17.4 18.1 Max 1.0 1.5 6.0 8.0 6.5 8.5 10 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 15 MinIII Max Unit TA 125C 11.5 15.0 8.5 10.5 12.0 18.0 22.0 19.3 12.0 16.0 19.2 1.5 2.0 7.5 9.5 10 pF pF pF ns ns ns ns ns ns ns ns
NLSF3T125
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.3 - 0.3 Max 0.8 - 0.8 3.5 1.5 Unit V V V V
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NLSF3T125
SWITCHING WAVEFORMS
3.0V GND tPZL Y 1.5V tPZH Y 1.5V tPHZ tPLZ HIGH IMPEDANCE VOL + 0.3V VOH - 0.3V HIGH IMPEDANCE
3.0V A tPLH 1.5V Y 1.5V tPHL GND VOH VOL
OE
1.5V
Figure 3.
Figure 4.
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST
TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL *
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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NLSF3T125
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50
D
A B
PIN 1 LOCATION
0.15 C 0.15 C TOP VIEW
0.10 C
16 X
0.08 C SIDE VIEW A1 C
16X
L
5
NOTE 5 4
16X
K
1 12
16X
0.10 C A B 0.05 C
NOTE 3
CCC CCC
(A3) D2 e
8 9 16 13
E
DIM A A1 A3 b D D2 E E2 e K L
A
SEATING PLANE
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
0.575 0.022
EXPOSED PAD
EXPOSED PAD
E2 e
3.25 0.128
1.50 0.059
b BOTTOM VIEW
0.50 0.02
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NLSF3T125
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PUBLICATION ORDERING INFORMATION
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NLSF3T125/D

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